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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
IDTQS34XST253 QUICKSWITCH(R) PRODUCTS HIGH-SPEED CMOS SYNCHROSWITCHTM 32:8 MUX/DEMUX WITH ACTIVE TERMINATORS
FEATURES:
- - - - - - - - - - - - - Enhanced N channel FET with no inherent diode to Vcc Bidirectional signal flow Flow-through pinout Zero propagation delay, zero ground bounce 8 banks of 4:1 Mux/Demux Port select synchronous to the clock Clock enable and asynchronous enable "Bus-hold" terminators on the Demux side Undershoot clamp diodes on all switch and control pins Asynchronous SEL option Break-before-make feature Available in 80-pin MillipaQ (Q3) Bus-hold eliminates floating bus lines and reduces static power consumption
DESCRIPTION:
The QS34XST253 is a high-speed CMOS 32:8 multiplexer/demultiplexer with active terminators (bus-hold circuits) on the demux side. It is organized as four independent dual 4:1 mux/demux blocks. Port selection and connection, controlled by SEL signals, can be either asynchronous or synchronous. In the synchronous mode, the A, B, C, or D port to Y port connection is updated on the rising edge of the input clock CLK. Once the port-to-port connection is made, data flow can be bi-directional with a typical 250ps propagation delay through the switch. Clock Enable, overriding Asynchronous Enable, and Asynchronous Select controls provide additional design flexibility. The bus-hold circuits latch the last data driven on the demux side, providing infinite hold time and glitch-free signal transitions. Synchronous controls and bus-hold ease timing constraints in many high speed data mux/ demux applications, such as bank interleaving. The QS34XST253 is available in the space-saving, 80-pin dual-in-line MillipaQ package. The QS34XST253 is characterized for operation at -40C to +85C.
APPLICATIONS
- Video, audio, graphics switching, muxing
FUNCTIONAL BLOCK DIAGRAM
R =
T
OEn0 OEn1 SELn0 SELn1 CLKn CLKENn SYNCn CONTR OL LOGIC
An0
T
Bn0 Yn0
T
Cn0
T
Dn0
T
An1
T
Bn1 Yn1
T
Cn1
T
Dn1
NOTE: One of four blocks shown.
T
INDUSTRIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
NOVEMBER 1999
DSC-5531/-
IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC A00 A01 B00 B01 C00 C01 D00 D01 GN D NC A10 A11 B10 B11 C10 C11 D10 D11 GN D NC A20 A21 B20 B21 C20 C21 D20 D21 GN D NC A30 A31 B30 B31 C30 C31 D30 D31 GN D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Vcc OE00 OE01 SEL00 SEL01 Y00 Y01 CLKEN0 CLK0 SYNC0 Vcc OE10 OE11 SEL10 SEL11 Y10 Y11 CLKEN1 CLK1 SYNC1 Vcc OE20 OE21 SEL20 SEL21 Y20 Y21 CLKEN2 CLK2 SYNC2 Vcc OE30 OE31 SEL30 SEL31 Y30 Y31 CLKEN3 CLK3 SYNC3
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) VTERM(3) VAC IOUT PMAX TSTG Description Supply Voltage to Ground DC Switch Voltage VS DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Output Current Maximum Power Dissipation (TA = 85C) Storage Temperature
(1) Unit V V V V mA W C
Max. - 0.5 to +7 - 0.5 to +7 - 0.5 to +7 -3 120 1.16 - 65 to +150
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc.
CAPACITANCE
(TA = +25OC, f = 1.0MHz, VIN = 0V, VOUT = 0V)
Pins Control Inputs Quickswitch Channels (Switch OFF) Demux Mux Typ. 4 6 13 Max. (1) 5 7 15 Unit pF pF pF
NOTE: 1. This parameter is guaranteed at characterization but not production tested.
PIN DESCRIPTION
Pin Names An0 - Dn0 An1 - Dn1 Yn0, Yn1 SELn0, SELn1 CLKn CLKENn OEn0, OEn1 SYNCn I/O I/O I/O I/O I I I I I Description Demux Ports Demux Ports Mux Ports Select Inputs Clock Clock Enable Output Enable Synchronous Selection Enable
MILLIPAQ TOP VIEW 2
IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Control Inputs SYNCn L L L L L L L H H H H H OEn0 L L L L H L H L L L L H OEn1 L L L L H L H L L L L H CLKn X X X X X CLKENn L L L L L H H X X X X X SELn0 L H L H X X X L H L H X SELn1 L L H H X X X L L H H X Yn0 An0 Bn0 Cn0 Dn0 Hold Previous Data (2) (Switch OFF) Hold Previous Mux connection (3) (Switch ON) Hold Previous Data (4) (Switch OFF) An0 Bn0 Cn0 Dn0 Hold Previous Data (Switch OFF) MUX Ports Yn1 An1 Bn1 Cn1 Dn1 Hold Previous Data (2) (Switch OFF) Hold Previous Mux connection (3) (Switch ON) Hold Previous Data (4) (Switch OFF) An1 Bn1 Cn1 Dn1 Hold Previous Data (Switch OFF)
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = Low-to-High Transition 2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connections can be changed by the SEL input. 3. The contents of the "Mux select register" are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will depend on the present data state of the input (Demux port). 4. The contents of the "Mux select register" are unchanged and the last value latch holds the previous data state.
CONTROL LOGIC (1)
OE n0
2:1 MUX SE Ln0
D
Q 2:1 MUX S0 To Bank n0 S w itches
CLKEN n CLK n SY N Cn
DE C OD E LO GIC AN D SW ITC H CO NTRO L
SE Ln1 2:1 MUX D Q
2:1 MUX
S1
To Ba nk n1 S w itches
OE n1
NOTE: 1. One of four blocks.
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIN RON IBHL IBHH IBH Parameter Input HIGH Voltage Input LOW Voltage Input Leakage Current (Control Inputs) Switch On Resistance (2) Input Hold Current (3,4) (A, B, C, D) Input Current (6) (A, B, C, D) Test Conditions Guaranteed Logic HIGH for Control Pins Guaranteed Logic LOW for Control Pins 0V VIN Vcc Vcc = Min., VIN = 0V, ION = 30mA Vcc = Min., VIN = 2.4V, ION = 15mA Vcc = 4.5V Switch OFF Vcc = Max. VIN = 0.8V VIN = 2V VIN = 0V or Vcc 0.8 < VIN < 2V Min. 2 -- -- -- -- 60 Typ.(1) -- -- -- 7 10 -- -- -- -- Max. -- 0.8 1 9 13 -- -- 20 500(5) A A Unit V V A
- 60
-- --
NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. Measured by voltage drop between A/B and Y pin at indicated current through the switch. 3. IBHL is the minimum sustaining "sink" current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in logic LOW state. 4. IBHH is the minimum sustaining "source" current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in logic HIGH state. 5. An external driver must provide at least IBH during transition to guarantee that the bus-hold input will change states. 6. IBH is the magnitude of the input current specified under two conditions: a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition. b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
TYPICAL ON RESISTANCE vs VIN AT VCC = 5V
16
RON
(ohms)
14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN
(Volts)
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICCQ ICC ICCD Parameter Quiescent Power Supply Current Power Supply Current per Control Input HIGH (2) Dynamic Power Supply Current per MHz(3) Test Conditions(1) VCC = Max., VIN = GND or Vcc, f = 0 VCC = Max., VIN = 3.4V, f = 0 VCC = Max., A/B/C/D and Y pins open Control Input Toggling at 50% Duty Cycle Max. 12 1.5 0.25 Unit A mA mA/MHz
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven control input. (VIN = 3.4V, Control Pins only.) A/B/C/D and Y pins do not contribute to Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B/C/D and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 5.0V 10% CLOAD = 50pF, RLOAD = 500 unless otherwise noted.
Symbol tPLH tPHL tSEC tHEC tCSO tASO tW tSCS tHCS tPZL tPZH tPLZ tPHZ Parameter Data Propagation Delay (1,2) A/B/C/D to Y, Y to A/B/C/D Clock Enable to Clock Setup Time Clock Enable to Clock Hold Time Clock to Switch Turn-On Delay (3) Asynchronous Select to Switch Turn-On Delay (3) Clock Pulse Width (High) SEL to Clock Setup Time SEL to Clock Hold Time Asynchronous Enable to Switch Turn-On Delay (3) Asynchronous Enable to Switch Turn-Off Delay (1,3) 3 0 0.5 0.5 3 3 0 1.5 1.5 Min. -- Typ. 0.25 -- -- -- -- -- -- -- -- -- Max. -- -- -- 7 7 -- -- -- 5.2 4.8 Unit
ns ns ns ns ns ns ns ns ns ns
NOTES: 1. This parameter is guaranteed but not production tested. 2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 3. Minimums guaranteed but not production tested.
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, DEMUX FUNCTION
SYNC tSEC tHEC CLK EN
CLK tSC S tHCS SEL tSC S tHCS
OE
Port Y
DATA 0
DATA 1 tPLH , tPHL
DATA 2
tCSO Port A INVALID DATA DATA 0 DATA 1 HOLD PR EVIOUS DATA, DATA 1 tPLH , tPHL tCSO Port D INVALID DATA DATA 1 DATA 2 HOLD PR EVIOUS DATA, DATA 2
EXAMPLE: PORT Y TO PORT A/PORT D
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, MUX FUNCTION
SY NC tSEC tHEC CLKEN
CLK tSCS tHCS tSCS tHCS
SEL0, SE L1
Port A
DATA1
DATA2
Port B
INV ALID D ATA tCSO tPLH, tPH L tCSO
DATA3
DATA4
tPLH, tPHL DATA3 DATA4
Port Y
INVALID D ATA
DAT A1
DATA2
EXAMPLE: PORT A/PORT D TO PORT Y
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - ASYNCHRONOUS MODE, MUX FUNCTION
SYNC
SEL
OE
Port A
INVALID DATA
DATA1 tPLH, tPHL
DATA2 tPLH, tPHL
Port D
INVALID DATA
DATA3 tPLZ, tPHZ DATA3 tPZL, tPZH
tASO Port Y INVALID D ATA DATA1 DATA2
DATA3
EXAMPLE: PORT A/PORT D TO PORT Y
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
ACTIVE TERMINATOR OR BUS-HOLD CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a "weak latch" with positive feedback. When connected to a TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is "disconnected" from the driver. When the output of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because the bus-hold circuit does not consume any static power.
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
IBH
+500
Sinking Current (+)
IBHL IBH IBHH Sourcing Current (-)
+60 +20 - 20 - 60
+60 IBHL
VT
Voltage +20 IBH - 20 IBH - 60 IBHL Vcc
VIL
VIH
IBH
- 500
0.8V
2V
VT Threshold Voltage 1.5V VIL .8 VIH 2V
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input voltage is increased from 0 volts, the input "sink" current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards Vcc, the input "source" current begins to decrease, reaching the lowest level at VIN = Vcc.
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IDTQS34XST253 HIGH-SPEED CMOS SYNCHROSWITCH 32:8 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
ID T Q S X X X XX D evice Type XX P ackage X P rocess
B lank
Industrial (-40C to +85C )
Q3
150 m il M illipaQ
34X S T253
H igh S peed C M O S S ynchroSw itch 32:8 M ux/D em ux w ith Active Term inators
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